As is known, the existence of means of ever-increasing performance for taking data into account and for processing it leads to applications being installed which cause ever-increasing volumes of data to be transmitted and processed at ever greater speeds. In particular, processors are using ever-increasing clock frequencies, e.g. about 200 MHz at present, but for reasons associated with physical constraints, such clock frequencies cannot be accepted by transmission links of the kind that can be connected to the input/output ports of the processors. As a general rule, whenever the processors of processor units in a given assembly are intercommunicating, provision is made to use much lower clock frequencies for interchanging data between them. It is therefore necessary to provide special measures for ensuring to as great an extent as possible that the processing capacity of the processors is not limited in practice by the insufficient capacity of the transmission means over which the processors communicate with one another.
In particular, there is a standard that originates from the IEEE known as the "IEEE standard for Futurebus+" concerning interconnection buses between processor units and issued by the IEEE. Nevertheless, because that standard seeks to be universal, it is difficult to obtain physical implementations that are simple and easy to integrate in sub-assemblies which are sometimes already rather complex. This difficulty of implementation applies not only to the bus itself but also to the connectors required for connection to the units that are to be served and to the interchange components of the bus. It is associated in particular with the high number of parallel links included in the bus, with the performance levels required of the various components, and with the constraints associated with the operation of a sub-assembly organized around the bus and the units served thereby.
Document EP 0 646 876 describes a system for interchanging data between data processor units, referred to as "agent units", in which the processors are interconnected by a common bus in an assembly comprising a plurality of units that are expected to accommodate a high level of data interchange traffic between one another. The data processor units comprise processors means, such as processors, which are interconnected by an external interchange bus common to the units, with bus sharing being orchestrated by an arbitrator. Each unit has storage means in which data is stored, at least temporarily, in an organized manner at determined addresses enabling the data to be written and/or read on demand. The data storage means constitute an interchange memory assembly distributed amongst said units, common to all of the units, and accessible by all of them via the interchange bus, each unit having a portion of the storage means of said assembly in the form of an interchange memory which is accessible firstly by the processor means of the unit and secondly by the processor means of the other units via the interchange bus.
However, that document does not deal with transmission and synchronization problems which arise while transferring data from one unit to another. The object of the invention is to solve those problems.